content long 18-May-2013 15:50:53

Solar Electron Proton Telescope (SEPT)

Electronics

Each detector is connected to one PDFE. The control of the four PDFEs, together with the interface to the central processor of the SEP package is managed by an ACTEL RT54SX32S FPGA. The analog electronics is divided into two totally independent parts as shown on the diagram above (one for each telescope). The PDFEs are also used as A-to-D converter for temperature and detector leakage current measurements. A pulse generator (one per telescope) can be used to check the front-end electronics during flight.

Figure 3: Electronics block diagram

Figure 4: View of the board stack (at the top the back of the digital board with two SRAMs)

The highly populated stack of 3 boards (analog board, digital board and EMI shield) is placed within the instrument base box. The different signals are routed from the detectors to the sidewall of the box via coax cables and then from the sidewall of the box to the analog board.

To gain in the integration of the electronics and as a growing trend, it was decided to use commercial parts for functionalities evaluated as non-critical and when no military or space-qualified equivalent was available. Hence, five parts (ADG704, ADG713, MAX892, ADP3300, TLC2262) were up-screened and together with the PDFE went through radiation testing. Total Ionizing Dose and heavy ions were studied at ESTEC (D/TOS-QCL) and have shown compliance with the mission constraints (12 krad with 75 mil Al for the 5 years extended mission). The potential latch-ups due to heavy ions are addressed thanks to a dedicated mitigation technique, also successfully tested at ESTEC.

Figure 5: Views of the top and bottom side of the analog board (Flight model)

 

Figure 6: View of the top of the analog board with the internal cables in the electronic box (Engineering model) compared to a one-euro coin


Last Update: 04 June 2009

For further information please contact: SciTech.editorial@esa.int

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